Modelling, Simulation and Verification of 4-phase Adiabatic Logic Design: A VHDL-Based Approach
- Submitting institution
-
The University of Westminster
- Unit of assessment
- 11 - Computer Science and Informatics
- Output identifier
- q9z32
- Type
- D - Journal article
- DOI
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10.1016/j.vlsi.2019.01.007
- Title of journal
- Integration: the VLSI Journal
- Article number
- -
- First page
- 144
- Volume
- 67
- Issue
- -
- ISSN
- 0167-9260
- Open access status
- Compliant
- Month of publication
- January
- Year of publication
- 2019
- URL
-
-
- Supplementary information
-
-
- Request cross-referral to
- -
- Output has been delayed by COVID-19
- No
- COVID-19 affected output statement
- -
- Forensic science
- No
- Criminology
- No
- Interdisciplinary
- No
- Number of additional authors
-
2
- Research group(s)
-
-
- Citation count
- 1
- Proposed double-weighted
- No
- Reserve for an output with double weighting
- No
- Additional information
- Behavioural description for functional verification of 4-phase adiabatic logic implementations has been impractical and approximate as well as inaccurate until the publication of this work, where a High Level Description Language (VHDL) based precise modelling and simulation verification approach has been demonstrated making it possible for the proliferation of adiabatic logic-family based designs in many low-power systems such as possibilities for novel deployments in NFC contactless cards.
The only alternative before this work with realistic modelling and simulation would have been low-level massively time-consuming SPICE-based simulations. This work is a step-change in CAD tools for multi-phase adiabatic logic implementations.
- Author contribution statement
- -
- Non-English
- No
- English abstract
- -
