Verifying Parallel Dataflow Transformations with Model Checking and its Application to FPGAs
- Submitting institution
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Heriot-Watt University
- Unit of assessment
- 11 - Computer Science and Informatics
- Output identifier
- 25937695
- Type
- D - Journal article
- DOI
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10.1016/j.sysarc.2019.101657
- Title of journal
- Journal of Systems Architecture
- Article number
- 101657
- First page
- -
- Volume
- 101
- Issue
- -
- ISSN
- 1383-7621
- Open access status
- Compliant
- Month of publication
- October
- Year of publication
- 2019
- URL
-
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- Supplementary information
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- Request cross-referral to
- -
- Output has been delayed by COVID-19
- No
- COVID-19 affected output statement
- -
- Forensic science
- No
- Criminology
- No
- Interdisciplinary
- No
- Number of additional authors
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5
- Research group(s)
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-
- Citation count
- 0
- Proposed double-weighted
- No
- Reserve for an output with double weighting
- No
- Additional information
- Models of computation and formal languages. Dataflow modelling and optimisation was a pivotal component in the EPSRC Rathlin (EP/K009931/1) project, bridging the gap between the RIPL image processing programming language and programmable FPGA hardware, with support from Xilinx (contact mblott@xilinx.com) who provided hardware and expertise. This led directly to new work for DSTL on algorithmic approximation and FPGA design (contact djnethercott@mail.dstl.gov.uk) as part of EP/S000631/ 1, "Signal Processing for the Information Age" (2018-23). Current work with ST Microelectronics (contact Brian.Stewart@st.com) to design embedded LiDAR systems on FPGAs uses these principles, achieving frame processing times of the order of 1ms (https://ieeexplore.ieee.org/document/8969177).
- Author contribution statement
- -
- Non-English
- No
- English abstract
- -
