A high-level design framework for the automatic generation of high-throughput systolic binomial-tree solvers
- Submitting institution
-
Imperial College of Science, Technology and Medicine
- Unit of assessment
- 12 - Engineering
- Output identifier
- 246
- Type
- D - Journal article
- DOI
-
10.1109/TVLSI.2017.2761554
- Title of journal
- IEEE Transactions on Very Large Scale Integration (VLSI) Systems
- Article number
- -
- First page
- 341
- Volume
- 26
- Issue
- 2
- ISSN
- 1063-8210
- Open access status
- Compliant
- Month of publication
- October
- Year of publication
- 2017
- URL
-
-
- Supplementary information
-
10.1109/TVLSI.2017.2761554
- Request cross-referral to
- -
- Output has been delayed by COVID-19
- No
- COVID-19 affected output statement
- -
- Forensic science
- No
- Criminology
- No
- Interdisciplinary
- No
- Number of additional authors
-
1
- Research group(s)
-
-
- Proposed double-weighted
- No
- Reserve for an output with double weighting
- No
- Additional information
- FPGAs (hardware compute accelerators) have been proposed for accelerating risk analysis algorithms, but the time and specialised knowledge needed to develop the hardware implementations has hindered adoption. This work presents the first mathematical framework for expressing financial algorithms which is guaranteed to automatically map into highly optimised parallel hardware, while simultaneously providing better performance than manual methods. This opens up high-performance risk analysis to non-hardware experts, allowing for hundreds of times faster and more accurate risk analysis for institutions and regulators. This work contributed to the award of a Leverhulme Fellowship to D. Thomas.
- Author contribution statement
- -
- Non-English
- No
- English abstract
- -