An investigation on border traps in III-V MOSFETs with an In0.53Ga0.47As channel
- Submitting institution
-
Liverpool John Moores University
- Unit of assessment
- 12 - Engineering
- Output identifier
- 1253
- Type
- D - Journal article
- DOI
-
10.1109/TED.2015.2475604
- Title of journal
- IEEE Transactions on Electron Devices
- Article number
- -
- First page
- 3633
- Volume
- 62
- Issue
- 11
- ISSN
- 0018-9383
- Open access status
- Out of scope for open access requirements
- Month of publication
- September
- Year of publication
- 2015
- URL
-
-
- Supplementary information
-
-
- Request cross-referral to
- -
- Output has been delayed by COVID-19
- No
- COVID-19 affected output statement
- -
- Forensic science
- No
- Criminology
- No
- Interdisciplinary
- No
- Number of additional authors
-
4
- Research group(s)
-
D - RCEEE
- Proposed double-weighted
- No
- Reserve for an output with double weighting
- No
- Additional information
- For the first time, this work separated different types of defects using innovative electrical methods and applied on alternative materials fabrication. The method has been adopted by the global test/measurement manufacturer Tektronix in its state-of-the-art equipment (Katie Wright, Marketing Director, Katie.Wright@keithley.com). The work led to an invited presentation at the Partner Technical Week (IMEC nanotechnology research centre, Belgium) to an audience including Intel and Samsung (Dr. Hiro Arimura, Senior Researcher, Hiro.Arimura@imec.be), and to a Newton Research Collaboration grant from the Royal Academy of Engineering (NRCP1516/4/77, £50k to LJMU, 2016-2017).
- Author contribution statement
- -
- Non-English
- No
- English abstract
- -