Device and Circuit Performance of the Future Hybrid III-V and Ge-Based CMOS Technology
- Submitting institution
-
Liverpool John Moores University
- Unit of assessment
- 12 - Engineering
- Output identifier
- 1279
- Type
- D - Journal article
- DOI
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10.1109/TED.2016.2603188
- Title of journal
- IEEE Transactions on Electron Devices
- Article number
- -
- First page
- 3893
- Volume
- 63
- Issue
- 10
- ISSN
- 0018-9383
- Open access status
- Compliant
- Month of publication
- September
- Year of publication
- 2016
- URL
-
-
- Supplementary information
-
-
- Request cross-referral to
- -
- Output has been delayed by COVID-19
- No
- COVID-19 affected output statement
- -
- Forensic science
- No
- Criminology
- No
- Interdisciplinary
- No
- Number of additional authors
-
3
- Research group(s)
-
D - RCEEE
- Proposed double-weighted
- No
- Reserve for an output with double weighting
- No
- Additional information
- As a key output of an EPSRC-funded project (EP/I010084/1, 2011-2014, £290k), the work proposes a novel hybrid III-V&Ge/Silicon nano-CMOS based on an Implant-Free Quantum-Well (IFQW) device architecture, a competitive advantage for nanoelectronics industry players. It has led to the increased interest in IFQW technology over the conventional Si for future CMOS technology nodes (Patent No. 8698129). This work has been used to boost the sub-16 nm CMOS technology at IMEC, the Belgian RD&I nanoelectronics and digital technologies hub (Meuris Marc, Program Manager, meurism@imec.be), and was disseminated to its core industrial partners, Intel, Samsung, Western Digital, TSMC, IBM and GlobalFoundries.
- Author contribution statement
- -
- Non-English
- No
- English abstract
- -
