Data Compression Device based on Modified LZ4 Algorithm
- Submitting institution
-
Queen's University of Belfast
- Unit of assessment
- 12 - Engineering
- Output identifier
- 147101856
- Type
- D - Journal article
- DOI
-
10.1109/TCE.2018.2810480
- Title of journal
- IEEE Transactions on Consumer Electronics
- Article number
- -
- First page
- 110
- Volume
- 64
- Issue
- 1
- ISSN
- 0098-3063
- Open access status
- Compliant
- Month of publication
- March
- Year of publication
- 2018
- URL
-
-
- Supplementary information
-
-
- Request cross-referral to
- -
- Output has been delayed by COVID-19
- No
- COVID-19 affected output statement
- -
- Forensic science
- No
- Criminology
- No
- Interdisciplinary
- No
- Number of additional authors
-
4
- Research group(s)
-
C - Electrical and Electronic
- Proposed double-weighted
- No
- Reserve for an output with double weighting
- No
- Additional information
- Data compression is commonly used in computer Solid State Drives (SSDs) to increase their performance , and, as such, hardware-based data compression designs are required. This paper studies the latest lossless data compression algorithm, LZ4. We modified LZ4 for real-time hardware implementation on an FPGA. Our architecture achieved throughputs of up to 1.92Gbps and compression ratios of up to 2.05, i.e. faster than previous LZ designs implemented on FPGAs. The significance is that it can improve the lifetime of consumer devices that use data compression, such as NAND flash-based SSDs. The work was conducted in-conjunction with the Texas A&M University.
- Author contribution statement
- -
- Non-English
- No
- English abstract
- -