A Low-Complexity Multiple Error Correcting Architecture Using Novel Cross Parity Codes Over GF (2m)
- Submitting institution
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Oxford Brookes University
- Unit of assessment
- 11 - Computer Science and Informatics
- Output identifier
- 185741151
- Type
- D - Journal article
- DOI
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10.1109/TVLSI.2014.2341631
- Title of journal
- IEEE Transactions on Very Large Scale Integration (VLSI) Systems
- Article number
- -
- First page
- 1448
- Volume
- 23
- Issue
- 8
- ISSN
- 1063-8210
- Open access status
- Out of scope for open access requirements
- Month of publication
- August
- Year of publication
- 2014
- URL
-
-
- Supplementary information
-
-
- Request cross-referral to
- -
- Output has been delayed by COVID-19
- No
- COVID-19 affected output statement
- -
- Forensic science
- No
- Criminology
- No
- Interdisciplinary
- No
- Number of additional authors
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3
- Research group(s)
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-
- Citation count
- 0
- Proposed double-weighted
- No
- Reserve for an output with double weighting
- No
- Additional information
- This innovative research, in collaboration with the Bristol University, is on low overhead Concurrent Error Detection and Correction in electronic hardware. This is much more challenging in digital circuits compared to memory where parity protection maybe sufficient. The first author was Dr Jabir’s PhD student who now heads the Microcontroller Series Development Department at Continental Teves, Germany. The technical knowhow is now applied in reliable electronic braking systems in automobiles. The IP is patented (No.9645886, 20140229786) and undergoing commercialisation and attracted funding from several sources e.g. MoD DSTL (No.CDE30507) which helped to develop proof of concept for commercialisation.
- Author contribution statement
- -
- Non-English
- No
- English abstract
- -