Efficient FPGA implementation of high-throughput mixed radix multipath delay commutator FFT processor for MIMO-OFDM
- Submitting institution
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Glasgow Caledonian University
- Unit of assessment
- 11 - Computer Science and Informatics
- Output identifier
- 33621802
- Type
- D - Journal article
- DOI
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10.4316/AECE.2017.01005
- Title of journal
- Advances in Electrical and Computer Engineering
- Article number
- -
- First page
- 27
- Volume
- 17
- Issue
- 1
- ISSN
- 1582-7445
- Open access status
- Compliant
- Month of publication
- February
- Year of publication
- 2017
- URL
-
-
- Supplementary information
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-
- Request cross-referral to
- -
- Output has been delayed by COVID-19
- No
- COVID-19 affected output statement
- -
- Forensic science
- No
- Criminology
- No
- Interdisciplinary
- No
- Number of additional authors
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4
- Research group(s)
-
-
- Citation count
- 3
- Proposed double-weighted
- No
- Reserve for an output with double weighting
- No
- Additional information
- This paper presents efficient OFDM FFT MIMO architecture on FPGA for communication systems.
The proposed custom pipeline obtains efficient implementation, including faster throughput and low hardware resources. Typically, as the data volume increases, so does hardware and power. Unlike other designs, this method maintained efficient design as data increases. This was cross-institutional work involving GCU, UWS, Qatar and Algeria universities. The work resulted in invited presentations to University of Medea and Qatar University. The work has influenced the design of current wireless FFT processors in 4G, WLAN and 5G from Beijing University with extension of the paper into nonpower-of-two DFTs.
- Author contribution statement
- -
- Non-English
- No
- English abstract
- -