Constructive Synthesis of Memory-Intensive Accelerators for FPGA From Nested Loop Kernels
- Submitting institution
-
Queen's University of Belfast
- Unit of assessment
- 12 - Engineering
- Output identifier
- 123922572
- Type
- D - Journal article
- DOI
-
10.1109/TSP.2016.2566608
- Title of journal
- IEEE Transactions on Signal Processing
- Article number
- -
- First page
- 4152
- Volume
- 64
- Issue
- 14
- ISSN
- 1053-587X
- Open access status
- Compliant
- Month of publication
- May
- Year of publication
- 2016
- URL
-
-
- Supplementary information
-
-
- Request cross-referral to
- -
- Output has been delayed by COVID-19
- No
- COVID-19 affected output statement
- -
- Forensic science
- No
- Criminology
- No
- Interdisciplinary
- No
- Number of additional authors
-
1
- Research group(s)
-
C - Electrical and Electronic
- Proposed double-weighted
- No
- Reserve for an output with double weighting
- No
- Additional information
- The work developed automatically translation of sequential code to FPGA accelerators constraining it to meet prescribed performance requirements, whilst accounting for constraints imposed by surrounding components, most notably off-chip off-chip DRAM. The work led to the award of a research grant by Keysight Laboratories to evaluate the use of the compiler for compilation of x86 code generated by their design tools, and to a Proof-of-Concept award by InvestNI, to develop the ideas for commercialisation.
- Author contribution statement
- -
- Non-English
- No
- English abstract
- -
