Fighting stochastic variability in a D-type flip-flop with transistor-level reconfiguration
- Submitting institution
-
University of York
- Unit of assessment
- 12 - Engineering
- Output identifier
- 55025975
- Type
- D - Journal article
- DOI
-
10.1049/iet-cdt.2014.0146
- Title of journal
- IET Computers and Digital Techniques
- Article number
- -
- First page
- 190
- Volume
- 9
- Issue
- 4
- ISSN
- 1751-8601
- Open access status
- Out of scope for open access requirements
- Month of publication
- June
- Year of publication
- 2015
- URL
-
-
- Supplementary information
-
-
- Request cross-referral to
- -
- Output has been delayed by COVID-19
- No
- COVID-19 affected output statement
- -
- Forensic science
- No
- Criminology
- No
- Interdisciplinary
- No
- Number of additional authors
-
3
- Research group(s)
-
B - Intelligent Systems and Nano-Science
- Proposed double-weighted
- No
- Reserve for an output with double weighting
- No
- Additional information
- The first example of generic optimization applied to trade-offs in nano-scale silicon design with multiple goals. It was the best paper 2016 in IET Computers & Digital Techniques (IET-CDT, https://digital-library.theiet.org/content/journals/iet-cdt/info/prize). The work resulted from the EPSRC PAnDA project (EP/I005838/1), and led to the EPSRC platform grant: Bio-inspired Adaptive Architectures and Systems (EP/K040820/1, £1M), the foundation of the York spin-out ngenics (ngenics.com), and collaborations with Cadence (Contact: Senior Engineer) and ARM (Contact: Senior Research Engineers).
- Author contribution statement
- -
- Non-English
- No
- English abstract
- -