Energy and Latency Optimization in NEM Relay-Based Digital Circuits
- Submitting institution
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University of Bristol
- Unit of assessment
- 11 - Computer Science and Informatics
- Output identifier
- 95853892
- Type
- D - Journal article
- DOI
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10.1109/TCSI.2014.2309752
- Title of journal
- IEEE Transactions on Circuits and Systems - I: Regular Papers
- Article number
- -
- First page
- 2348
- Volume
- 61
- Issue
- 8
- ISSN
- 1549-8328
- Open access status
- Out of scope for open access requirements
- Month of publication
- August
- Year of publication
- 2014
- URL
-
-
- Supplementary information
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-
- Request cross-referral to
- -
- Output has been delayed by COVID-19
- No
- COVID-19 affected output statement
- -
- Forensic science
- No
- Criminology
- No
- Interdisciplinary
- No
- Number of additional authors
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9
- Research group(s)
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D - Fundamentals of Computing
- Citation count
- 10
- Proposed double-weighted
- No
- Reserve for an output with double weighting
- No
- Additional information
- This is the first work that addresses implementation of energy-efficient nanoelectromechanical relay-based circuits while overcoming inherent latency limitations of relays. It describes how to model previously unconsidered but critical aspects of relay operation and mitigates them through design. This work was carried out within a prestigious international team comprising IBM Zurich, STMicroelectronics Agrate, EPFL and KTH led by Pamunuwa. This work contributed significantly to two subsequent grant awards, NEMICA (No. 61931-453231, £794k) funded by Innovate and NEMRAD (CDE38104, £120k), funded by DSTL UK. It also led to an invited talk at the UK-Japan Silicon Nanoelectronics & Nanotechnology Symposium in 2015.
- Author contribution statement
- -
- Non-English
- No
- English abstract
- -