Stage-Dependent DSP Operation Range Clipping-Induced Bit Resolution Reductions of Full Parallel 64-Point FFTs Incorporated in FPGA-Based Optical OFDM Receivers
- Submitting institution
-
Bangor University / Prifysgol Bangor
- Unit of assessment
- 12 - Engineering
- Output identifier
- UoA12_69
- Type
- D - Journal article
- DOI
-
10.1109/JLT.2016.2584386
- Title of journal
- Journal of Lightwave Technology
- Article number
- -
- First page
- 3752
- Volume
- 34
- Issue
- 16
- ISSN
- 0733-8724
- Open access status
- Not compliant
- Month of publication
- June
- Year of publication
- 2016
- URL
-
-
- Supplementary information
-
-
- Request cross-referral to
- -
- Output has been delayed by COVID-19
- No
- COVID-19 affected output statement
- -
- Forensic science
- No
- Criminology
- No
- Interdisciplinary
- No
- Number of additional authors
-
7
- Research group(s)
-
-
- Proposed double-weighted
- No
- Reserve for an output with double weighting
- No
- Additional information
- The FFT is a core building block of a wide diversity of DSP-based ASICs, and it determines the ASIC's performance, logic resource usage and cost. A ground-breaking DSP algorithm is proposed, which significantly reduces the FFT complexity and simultaneously improving its performance/accuracy. The technique leads to fundamental changes of how to conduct the real-time FFT. As ASICs are the hearts of modern technologies, the proposed technique has established a solid platform enabling Bangor to win a £3m NWGD project, in which Bangor will work with Fujitsu to develop and commercialise FFT-based ASIC chips and IP cores.
- Author contribution statement
- -
- Non-English
- No
- English abstract
- -
