Parallel Hardware Merge Sorter
- Submitting institution
-
The University of Manchester
- Unit of assessment
- 11 - Computer Science and Informatics
- Output identifier
- 51267379
- Type
- E - Conference contribution
- DOI
-
10.1109/FCCM.2016.34
- Title of conference / published proceedings
- 24th IEEE International Symposium on Field-Programmable Custom Computing Machines, FCCM 2016
- First page
- 95
- Volume
- -
- Issue
- -
- ISSN
- -
- Open access status
- -
- Month of publication
- August
- Year of publication
- 2016
- URL
-
-
- Supplementary information
-
-
- Request cross-referral to
- -
- Output has been delayed by COVID-19
- No
- COVID-19 affected output statement
- -
- Forensic science
- No
- Criminology
- No
- Interdisciplinary
- No
- Number of additional authors
-
3
- Research group(s)
-
A - Computer Science
- Citation count
- 20
- Proposed double-weighted
- No
- Reserve for an output with double weighting
- No
- Additional information
- "A highly parallel hardware sorter which outperforms traditional sequential operation by orders of magnitude is presented. Even difficult ''skewed'' problems are sorted up to 160x faster than state of the art sequential sorters. This has been demonstrated with a functional FPGA implementation.
The architectural principle allows sorting of very high speed real-time data streams whilst keeping internal operating speed and power within manageable limits.
Following FCCM2016, this paper established a research agenda for high throughput sorting. The approach has been widely adopted for lower resources and lower latency sorting as evidenced by publications at FCCM2017, FCCM2018 and other venues."
- Author contribution statement
- -
- Non-English
- No
- English abstract
- -
