Least Upper Delay Bound for VBR Flows in Networks-on-Chip with Virtual Channels
- Submitting institution
-
University of East London
- Unit of assessment
- 11 - Computer Science and Informatics
- Output identifier
- 23
- Type
- D - Journal article
- DOI
-
10.1145/2733374
- Title of journal
- ACM Transactions on Design Automation of Electronic Systems
- Article number
- -
- First page
- 1-33
- Volume
- 20
- Issue
- 3
- ISSN
- 1084-4309
- Open access status
- Out of scope for open access requirements
- Month of publication
- -
- Year of publication
- 2015
- URL
-
-
- Supplementary information
-
-
- Request cross-referral to
- -
- Output has been delayed by COVID-19
- No
- COVID-19 affected output statement
- -
- Forensic science
- No
- Criminology
- No
- Interdisciplinary
- No
- Number of additional authors
-
2
- Research group(s)
-
2 - Enterprise Computing
- Citation count
- 6
- Proposed double-weighted
- No
- Reserve for an output with double weighting
- No
- Additional information
- This paper proposes a new methodology to find out if the design of communication networks between devices on a chip can meet the criteria of real-time applications. This paper presents and proves new technical theorems based on Network Calculus to build a mathematical model for designers to analyse and evaluate the worst-case delay boundaries for on-chip networks. This journal paper is the extended version of an article presented at DATE conference, which has been cited in the 214373 ArtistDesign NoE Report [1]. ArtistDesign is a European research community in Embedded Systems Design [2].
[1] http://www.artist-embedded.org/docs/Events/2012/ArtistDesign_Y4_Review/Deliverables/D13-6-2-Y4_Platform_and_MPSoC_Analysis.pdf
[2] http://www.artist-embedded.org/artist/-About-the-ArtistDesign-NoE-.html
- Author contribution statement
- -
- Non-English
- No
- English abstract
- -