Mixed-size concurrency : ARM, POWER, C/C++11, and SC
- Submitting institution
-
University of St Andrews
- Unit of assessment
- 11 - Computer Science and Informatics
- Output identifier
- 252050252
- Type
- E - Conference contribution
- DOI
-
10.1145/3009837.3009839
- Title of conference / published proceedings
- Proceedings of the 44th annual ACM-SIGPLAN Symposium on Principles of programming languages (POPL 2017)
- First page
- 429
- Volume
- 52
- Issue
- 1
- ISSN
- 0362-1340
- Open access status
- Compliant
- Month of publication
- January
- Year of publication
- 2017
- URL
-
-
- Supplementary information
-
-
- Request cross-referral to
- -
- Output has been delayed by COVID-19
- No
- COVID-19 affected output statement
- -
- Forensic science
- No
- Criminology
- No
- Interdisciplinary
- No
- Number of additional authors
-
8
- Research group(s)
-
B - Systems
- Citation count
- 3
- Proposed double-weighted
- No
- Reserve for an output with double weighting
- No
- Additional information
- Programmers write programs accessing memory using different sized accesses (bytes, words, longs etc), but before this, no formal model used for verification could handle this feature in the concurrent case. It also showed that a commonly believed simplification -- that inserting barrier instructions could always make programs behave simply (technically, sequentially consistent) -- was untrue, and directly led ARM to make a significant simplification to their published architecture description, and IBM POWER to consider a similar simplification.
Senior Engineer, IBM
-- see letter as part of submitted impact case.
- Author contribution statement
- -
- Non-English
- No
- English abstract
- -
