RIPL: A Parallel Image Processing Language for FPGAs
- Submitting institution
-
Heriot-Watt University
- Unit of assessment
- 11 - Computer Science and Informatics
- Output identifier
- 16615354
- Type
- D - Journal article
- DOI
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10.1145/3180481
- Title of journal
- ACM Transactions on Reconfigurable Technology and Systems
- Article number
- 7
- First page
- -
- Volume
- 11
- Issue
- 1
- ISSN
- 1936-7406
- Open access status
- Compliant
- Month of publication
- March
- Year of publication
- 2018
- URL
-
-
- Supplementary information
-
-
- Request cross-referral to
- -
- Output has been delayed by COVID-19
- No
- COVID-19 affected output statement
- -
- Forensic science
- No
- Criminology
- No
- Interdisciplinary
- No
- Number of additional authors
-
5
- Research group(s)
-
-
- Citation count
- 3
- Proposed double-weighted
- No
- Reserve for an output with double weighting
- No
- Additional information
- RIPL was a pivotal technology in the EPSRC Rathlin (EP/K009931/1) project, bridging the gap between image processing experts and code developers at Heriot-Watt University and FPGA designers at Queen's University Belfast, with support from Xilinx (contact mblott@xilinx.com) who provided hardware and expertise. This led directly to new work for DSTL on algorithmic approximation and FPGA design (contact djnethercott@mail.dstl.gov.uk) as part of EP/S000631/ 1, "Signal Processing for the Information Age" (2018-23). Current work with ST Microelectronics (contact Brian.Stewart@st.com) to design embedded LiDAR systems on FPGAs uses these principles, achieving frame processing times of the order of 1ms (https://ieeexplore.ieee.org/document/8969177).
- Author contribution statement
- -
- Non-English
- No
- English abstract
- -
