An Event-Triggered Programmable Prefetcher for Irregular Workloads
- Submitting institution
-
University of Edinburgh
- Unit of assessment
- 11 - Computer Science and Informatics
- Output identifier
- 155855707
- Type
- D - Journal article
- DOI
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10.1145/3296957.3173189
- Title of journal
- ACM Sigplan Notices
- Article number
- -
- First page
- 578
- Volume
- 53
- Issue
- 2
- ISSN
- 0362-1340
- Open access status
- Technical exception
- Month of publication
- March
- Year of publication
- 2018
- URL
-
-
- Supplementary information
-
-
- Request cross-referral to
- -
- Output has been delayed by COVID-19
- No
- COVID-19 affected output statement
- -
- Forensic science
- No
- Criminology
- No
- Interdisciplinary
- No
- Number of additional authors
-
1
- Research group(s)
-
A - Computer Systems
- Citation count
- 4
- Proposed double-weighted
- No
- Reserve for an output with double weighting
- No
- Additional information
- This paper was published in ASPLOS, the top international venue for interdisciplinary architecture and programming languages research (18% acceptance rate). It resulted in a joint patent with Arm (Event triggered programmable prefetcher, GB2544474B / WO2017085450A1). The heterogeneous architecture, used here for prefetching, and which surrounds a main compute core with many smaller parallel processing units, was reused for future work on Fault Tolerance (DSN 2018/2019 and a further joint patent with Arm, GB2555628B / WO2018083441A1), and Security (ASPLOS 2020). The security research using the same architecture inspired a grant, Programmable Real-Time Security, funded by Huawei in 2020 for £732,581.
- Author contribution statement
- -
- Non-English
- No
- English abstract
- -